1. Field of the Invention
The present invention relates to integrated circuit memory, and decoding structures utilized in such devices.
2. Description of Related Art
In high density memory, the arrays of memory cells are often divided into a plurality of blocks of memory cells. Each block of memory cells may include local word lines, requiring corresponding local word line drivers. In these configurations, there can be a global word line driver which drives a set of global word lines for a column of blocks in the array. Each word line in the set of global word lines is set according to the operation being applied to the selected blocks, such as read, program, and erase for high density flash devices. Some operations can require high voltages and some can require negative voltages for some types of memory devices. As a result, word line drivers are required that can meet difficult high voltage and negative voltage operating parameters.
In such high density arrays including a large number of local word line drivers, the area required for implementation of the local word line drivers can become significant overhead and implementation cost of the devices.
It is desirable to provide technology which can reduce the area requirements for local word line drivers, and for similar structures, while meeting the difficult specifications required for such devices.